library verilog;
use verilog.vl_types.all;
entity pmi_mult is
    generic(
        pmi_dataa_width : integer := 8;
        pmi_datab_width : integer := 8;
        module_type     : string  := "pmi_mult";
        pmi_sign        : string  := "on";
        pmi_additional_pipeline: integer := 1;
        pmi_input_reg   : string  := "on";
        pmi_output_reg  : string  := "on";
        pmi_family      : string  := "EC";
        pmi_implementation: string  := "LUT"
    );
    port(
        DataA           : in     vl_logic_vector;
        DataB           : in     vl_logic_vector;
        Clock           : in     vl_logic;
        ClkEn           : in     vl_logic;
        Aclr            : in     vl_logic;
        Result          : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_dataa_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_datab_width : constant is 1;
    attribute mti_svvh_generic_type of module_type : constant is 1;
    attribute mti_svvh_generic_type of pmi_sign : constant is 1;
    attribute mti_svvh_generic_type of pmi_additional_pipeline : constant is 1;
    attribute mti_svvh_generic_type of pmi_input_reg : constant is 1;
    attribute mti_svvh_generic_type of pmi_output_reg : constant is 1;
    attribute mti_svvh_generic_type of pmi_family : constant is 1;
    attribute mti_svvh_generic_type of pmi_implementation : constant is 1;
end pmi_mult;
